1. Field of the Invention
The present invention relates to semiconductor processing. More particularly, the present invention relates to fabricating epitaxial layer of a semiconductor. Still more particularly, the present invention relates to a method for processing epitaxial layers of a semiconductor for reducing soft errors and a resulting semiconductor and semiconductor wafer.
2. Description of Related Art
A “soft error” is a glitch or error in the functioning of a semiconductor device. The frequency of the occurrence of soft errors is described as the soft error rate (SER). Soft errors are particularly problematic with respect to memory devices, but many types of semiconductor devices are prone to soft error glitches. Soft errors occur randomly and are not normally catastrophic. Typically, soft errors are not due to any permanent physical defects in the memory or device, and when they occur, they do not normally damage the device.
To understand the nature of soft errors, one must recall that integrated circuits (ICs) manipulate charge in order to perform logic functions, process instructions, store data, etc. As device geometries decrease, the amount of charge used for processing and storage also decreases. A certain threshold of charge, or critical charge, must be present (or absent) for the device to recognize that the charge exists (or does not exist). If stray, unwanted charge (or transient charge) is able to add or subtract from the charge being used to perform functions or store data. It is possible that the critical charge can be converted from one logic state to another (from a high to a low, or a low to a high) without receiving or contrary to internal instruction signals. Importantly, soft errors are caused by forces outside of the designer's control.
Soft errors result when a charged particle strikes the semiconductor device, usually a memory structure or a memory-type element. Soft errors may not result from a direct hit on the device itself, but often result from the particle traversing a semiconductor in the vicinity of a device fabricated within the semiconductor. Soft errors occur when a bit (or any dynamically stored charge in a logic circuit) in a memory cell flips as a result of a charged particle penetrating (within the vicinity of) one or more of the memory cell storage locations. The charge (electron-hole pairs) generated by the interaction of an energetic charged particle with the semiconductor atoms corrupts the stored information in the memory cell. Generally, when the charged particle crosses a transistor junction, gate or adjacent arrays, an aberrant charge is created.
Charged particles can come directly from radioactive materials and cosmic rays, or indirectly as a result of high-energy particle interaction with the semiconductor itself. As high-energy cosmic rays and solar particles react with the upper atmosphere, high-energy protons and neutrons are generated and shower to the ground. Neutrons are particularly troublesome as they can penetrate most man-made construction (a neutron will easily pass through 5 feet of concrete), but it is generally accepted that alpha particles present the greater problem as they are much more prevalent than other harmful cosmic particles in the atmosphere. The concentration of high energy cosmic particles varies with both latitude and altitude. For example, London, U.K. experiences approximately four times the amount of cosmic particles than does southern Los Angeles, Calif., U.S.A. Similarly, Denver, Colo., U.S.A., which has an elevation of over 5,000 ft. above sea level, receives approximately 1.5 times the amount as does San Francisco, Calif. U.S.A. which is situated near sea level. However, soft error sources may also be terrestrial in origin. For example, one source of alpha particles is the packaging materials of integrated circuits in which trace amounts of alpha producing radioactive isotopes are present. Bump materials used in the certain Flip-Chip packaging techniques have also been recently identified as also containing alpha particle sources.
Once a soft error has occurred, the only remedy is to either write new data to the invalid memory area, if the area can be identified, or restart the system using the memory, thereby resetting all memory locations to known states. Many systems can tolerate some level of soft errors. For example, memory errors which result in missing or wrong colored bits on a display screen are rarely noticed in video applications. However, such is not the case when the affected memory elements are used to control the functionality of the device, such as in an SRAM FPGA. In those cases, soft errors can have a much more serious impact and lead not only to corrupt data, but also to a loss of functionality and system critical failures.
The SER phenomenon was first noticed in DRAMs, SRAM and SRAM-based devices are also subject to the same effects. Unlike capacitor-based DRAMs, SRAMs are constructed of cross-coupled devices which have far less capacitance in each cell. The lower the capacitance of a cell, the greater the likelihood of an upset.
Some of the fundamental aspects of the SER problem may be better understood in conjunction with the description of the device in FIG. 1. FIG. 1 is a diagram of a portion of a typical semiconductor and is not meant as a preferred description, nor is the figure intended to limit the application of the present invention in any way. FIG. 1 depicts semiconductor 100 as an impurity layer formed or grown on substrate 102 which consists of epitaxial layer 104. One of ordinary skill in the art would readily understand that epitaxial layer 104 may be grown with the demands of different applications in mind, e.g., power devices require low-doped (1013 to 1015 cm−3), thick (30 to 100 μm) layers whereas high-frequency devices require thin layers (<0.2 μm to several μm) with moderate (1015 cm−3) to heavy doping (1019 cm−3). As depicted in the diagram, device 108 has been fabricated in an upper layer of epitaxial layer 104 of semiconductor 100 using any well-known device fabrication process. Device layer 106 may be formed, or grown, epitaxially as described at http://www.globitech.com/epitaxy.htm. The layer in which devices are fabricated is commonly referred to as a device layer, in the depicted example, device layer 106. With regard to the specific example, device 108 is afield effect transistor (FET) which is well known to artisans in the art as consisting of three regions, labeled source S, gate G and drain D. Gate G is a sandwich consisting of the underlying material, in this case the P-epitaxial layer 104 forming P-channel 105; thin insulating layer 109 (usually silicon dioxide); and upper metal layer 107. In FIG. 1, the semiconductor material in the source and drain regions 101 and 103 are doped with N-type material which is a different type of material than in the region under the gate, thus an NPN MOSFET; however, but device 100 could be a PNP with P-type source and drain and an N-type gate.
Traversing the layers of semiconductor 100 is particle 110, in this case shown as an particle, but it could be any type of fast moving or charged particle, such as a neutron, an alpha particle or gamma ray. Notice that particle 110 does not directly contact device 108. Upon making contacting with the surface, particle 110 causes track 111 of stray charges 112 to be created consisting of electron-hole pairs of a given length and lifetime, depicted as electrons (−) and holes (+). As mentioned, particle 110 can originate from any number of sources. A particle can enter a semiconductor at almost any angle depending only on the direction of the path of the particle relative to the orientation of the semiconductor. Particle 110 is depicted in the illustration as entering the semiconductor at an incident angle with respect to the surface and incident angle is depicted as being sufficiently large such that particle 110 penetrates device layer 106, epitaxial layer 104 and substrate 102 before it is absorbed or exits semiconductor 100. It might be expected that the electrons and holes recombine almost instantly, and in fact, most do. However, some of dislodged carriers 112 often do not recombine instantaneously, but instead migrate to nodes of the opposite potential to which they are attracted. Likely targets include capacitor plates, bitlines, latching nodes, bootstrap nodes and sense nodes. This occurrence can result in a change in state (“upset”) of the corresponding circuit, a soft error, especially in circuits utilizing very small capacitances transferring very small charges. One of the most significant discoveries in understanding how charged particles, such as alpha-particles, upset circuits was that charges 112 developed along particle 110's track distort local electric fields such that charges 112 are pulled back up track 110 toward the semiconductor surface rather than diffusing into the semiconductor bulk in an effect called “funneling.” This greatly increases the harmful SER.
The soft error metric is failure-in-time (FIT). Often, a typical soft error rate is given as 1,000 FITs which means that one device will fail every 144 years. However, with current 0.13-micron technology, error rates of 10,000 or 100,000 FITs per megabit have been reported thus increasing the frequency of error in a single device down to weeks or months from a typical failure rate of 144 years. Additionally, and as mentioned above, the failure rate may also change depending on the latitude and altitude in which a particular device is operating. For example, the International Business Machine Corporation (IBM) has discovered that SRAM tested at 10,000 feet above sea level will record SERs that are 14 times the rate tested at sea level. Therefore, SER poses a significant problem in non-terrestrial applications such as air and spacecraft control and communications devices.
Historically, SER reduction efforts have been in three general areas: packaging; circuit design and layout; and semiconductor fabrication. Initially, it has been understood that soft errors of a terrestrial origin are much easier to prevent than those having a cosmic origin. These are due almost entirely to alpha particles. Their effect can be minimized by: 1) limiting their source of the alpha particles by using packaging materials with low uranium or thorium contaminants; 2) using coatings over the die to block the alpha particles; and finally; 3) by making the memory bit less vulnerable to particle hit. However, for particles of non-terrestrial origin resulting from cosmic rays, the primary way to limit soft errors at the chip level is by making the memory bit less vulnerable to the hit.
Alpha particles typically travel approximately 20 to 25 μm before they are stopped. This leads to the conclusion that the source of alpha particles must be relatively close to the memory bits themselves, such as the chip metalization, die coats, adhesives, package lead frames, and mold compounds. Thus, by using higher quality packaging materials, the number of potential soft error rates can be realized. In addition to selecting higher quality packaging, manufacturers often coat the chip with low emission die coats to take advantage of the limited range that alpha particles can travel before being stopped. However, these solutions add costs to the chip fabrication and do little to increase SER reduction resulting from cosmic particles.
Prior art SER reduction techniques have recognized that SER resulting cosmic particles can be virtually eliminated at a subterranean depth of 60 feet being shielded by solid rock. In certain situations, devices operated in extremely mission critical applications may be assured of extremely low SERs by operating the devices subterranean. Rarely is the subterranean operation of devices practicable, regardless of their mission. Pragmatically, mission critical devices should be operated at lower attitudes; basements offer the most practical protection, and if feasible, in locations having lower geographic latitudes.
The prior art suggests making the memory bit less vulnerable to particle hit primarily by selecting optimal circuit design and layout alternatives. One technique involves utilizing memory with increased capacitance in a storage node SER robustness. Increasing a node capacitance can exponentially reduce the probability of an SER on that node. Another is to select memory cell designs that use relatively higher voltage. The higher the charge, the better the SER resistance. The array nodes for 0.17 um trench processes are nominally 1.8 volts and are higher than that present in other technologies, which can use voltages of 1.5 volts and lower. The use of shallow wells in order to reduce the collection efficiency of a charge created by a radiating particle is another technique, as well as selecting cell designs with lower collection efficiency and smaller array size. For example, a DRAM cell has one transistor whose junctions can serve as a charge collector, while SRAM architectures will have both more and larger junctions associated with each bit of data. Increasing the signal margin (the ratio of cell capacitance to bitline capacitance), thereby resulting in higher signal-to-noise ratio into a sense amplifier. Finally, the prior art suggests that the use of error correction code (ECC) wherein one bit errors are errors are not only detected, but also corrected on the fly. For this reason, ECC is also commonly referred to as error checking and correcting and has a dramatic impact on reducing the effects of SER.
Soft errors continue to become a growing concern. The most effective defense suggested by the prior art seems to be directed to the detection of these errors and subsequent correction. This has been accomplished with on-chip circuitry that continuously performs logic tests to determine whether a logic node has been converted erroneously. Once an error is detected, this circuitry must also perform the correction. The difficulty in this approach is becoming apparent as device geometries continue to decrease. The sensitivity to transient charge due to decreased critical charge, and the increased complexity and density of leading edge IC device designs, make error detection and correction circuitry increasingly prohibitive in terms of complexity and silicon real estate.
Several “design-around” solutions for handling the stray carrier charges have been proposed in the prior art, including the formation of retrograded well structures as described in U.S. patent application Ser. No. 2002/0020888A1 filed on Feb. 21, 2002 by Yamashita et al. Yamashita describes a process for controlling soft errors based on electrons, with a retrograde well having a high doping concentration formed over a second layer with a low doping concentration which, in turn, has been formed over a substrate doped with a concentration between that of the well and the second layer. The wells are doped in a typical fashion by forming a mask of a patterning of resist for the active well region, onto another layer in which ions have been implanted. This layer may require thermal annealing. The resulting potential formed inside the well near the interface of the second layer acts as a barrier to stray charges, thereby reducing the SER. Of course, devices requiring wells of different types and concentrations are most probably handled in separate processing steps which increase processing time and cost.
Other shortcomings of the retrograded well solution for the reduction of SER will be apparent with the description of FIGS. 2-4 in which numbering is consistent throughout for designating like parts. FIGS. 2-4 are spreading resistance profiles (SRPs) which each graphically illustrates dopant concentration (atoms/cm3) in the vertical axis plotted against depth from the surface of a wafer (x10−6 (microns)) in the horizontal axis. FIG. 2 is a diagram of a SPR illustrating the profile of dopant concentrations measured over the depth of semiconductor 100. Semiconductor 100 is represented in the graph as having substrate layer 202, epitaxial layer 204 and well 213 (designated 102, 104 and 113, respectively in FIG. 1). Notice that depicted in FIG. 2 are two separate dopant profile curves; semiconductor dopant profile curve 230 and well diffusion dopant profile 232. Semiconductor dopant profile curve 230 is taken along semiconductor section of a A-A′ cross-section of semiconductor 100 which traverses epitaxial layer 104, including device layer 106, and substrate 102. Well diffusion dopant profile curve 232, on the other hand, is taken along semiconductor section of a B-B′ cross-section of semiconductor 100 which traverses only well 113 fabricated in device layer 106 of epitaxial layer 104 over substrate 102.
Doping semiconductor layers is typically performed with a constant dopant concentration throughout a given layer as can be realized from semiconductor dopant profile curve 230 which illustrates a constant dopant rate applied through substrate 202 and a lower, but constant, dopant rate applied across well depth 213. This is typical of many semiconductor applications and is shown separately in FIG. 7. Notice from FIG. 2 that semiconductor dopant profile curve 230 indicates an abrupt change in dopant concentration at the epitaxial/substrate boundary at an approximate depth of 6 microns. Typically, it is expected that an electrostatic field is associated with the interface as a result of the change in concentrations of dopants. The resulting electric field has been reported to provide a reduction in SER under certain circumstances. Mohan Rao describes several techniques for reducing SER by constructing semiconductor layer interfaces which may create an “aiding” electrostatic field to push minority carriers into bulk substrate in U.S. non-provisional patent application Ser. No. 10/244,946 entitled “Semiconductor Devices with Soft Error Protection and Systems and Methods Using the Same” filed on Sep. 17, 2002 and incorporated by reference herein in its entirety.
Another known technique in semiconductor manufacturing introducing dopants into the wafer surface can result in a natural graded dopant profile below the dopant diffusion well as illustrated by well diffusion dopant profile curve 232. For the purposes herein, a graded dopant profile may be produced as a result of an effective change in dopant concentration over a depth interval. Thus, rather than an abrupt change in dopant concentrations, as is present at many boundaries between semiconductor layers, a grading describes a rate dopant of change. Specifically, semiconductor 100 represented in the present figure has a dopant concentration of slightly below 1015 atoms/cm3 (e.g., approximately 0.8×1015 atoms/cm3) over non-well surface areas. Dopant concentrations remain a constant 0.8×1015 atoms/cm3 vertically in the non-well regions until the approximate depth of the epitaxial layer 204 where the dopant concentration increases until reaching an exemplary concentration of slightly below 1018 atoms/cm3 where it remains constant throughout the depth of substrate 202. In well areas of the semiconductor, dopant atoms are diffused into the well usually through high temperature, high pressure well diffusion process, represented in FIG. 2 as well diffusion curve 232. Notice that the doping profile of well 113 (FIG. 1) is higher near the surface, approximately 1017 atoms/cm3 but decreases with the depth of well 113 until no dopant is present, which defines the furthermost extent of well 113. Conventional wells are formed by implanting dopants and diffusing them to the desired depth. However, they diffuse laterally as well as vertically, which reduces packing density resulting in a dopant concentration curve with the character of well diffusion curve 232.
Applicants have discovered that a weak electrostatic field is associated with the graded dopant profile typical of many well diffusion doping processes. Moreover Applicants have applied this well diffusion dopant profile to the problem of SER to force minority carriers created by a charged particle, such as an alpha particle or gamma ray, which interacts with the semiconductor leaving a track of electron-hole pairs of a given length and lifetime.
FIG. 3 is a graph illustrating the profile of dopant concentrations over the depth of semiconductor 100 having a physical structure that is similar to that described above with regard to FIG. 2, i.e. having substrate layer 302, epitaxial layer 304 and well 313 (designated 102, 104 and 113, respectively in FIG. 1). Semiconductor dopant profile curve 330 taken along semiconductor section of a A-A′ cross-section of semiconductor 100 is also similar to semiconductor dopant profile 230 from FIG. 2. The character of dopant profile 330 and well diffusion curve 332 generally corresponds to curves 230 and 232, respectively, although the absolute dopant concentrations vary slightly between the graphs. However, in contrast to the previously discussed dopant profile, well 113 is shown to have three dopant profile curves, well diffusion dopant profile curve 332, which is identical to well diffusion dopant profile curve 232, retrograde well dopant profile 334 and resultant well dopant profile 336. Here, since a high-energy implant is used to place the dopants at the desired depth without further diffusion, much less lateral spread will occur. Such high-energy implants also bury the peak of the impurity profile to a certain depth within the substrate, and the concentration of the impurity decreases as it approaches the wafer surface. Wells with such profile are called retrograde wells. Resultant well dopant profile 336 results from a dopant processes (ion implants) that specifically address soft errors. By exaggerating the dopant level and providing a peak concentration well below the wafer surface (retrograded well) forming retrograde well dopant profile 334, a larger dopant grading can be achieved over the well diffusion doping process. Moreover, when combined with well diffusion, resultant well dopant profile 336 is realized which can further assist in soft error reduction in the region below the retro-graded well.
Turning now to FIG. 4, the benefit of retrograde well implant is graphically illustrated as margin 452 which is a measure of the difference in resultant well dopant profile 436 and semiconductor dopant profile 430. Margin 452 suggests that the retrograde well implant provides a qualitative reduction in SER over non-retrograded semiconductor structures such as semiconductor dopant profile curve 430 which is taken along semiconductor section of a A-A′ cross-section of semiconductor 100.
However, even though the utilization of retrograded implant for SER reduction provides some measurable benefit, it also suffers from a major drawback. First, retrograded well ion implant for SER reduction is a “design in” solution meaning that the total effect of the well retrograde on the device must be determined prior to implementing retrograde implantation as a solution. Not every device is compatible with a retrograded well and other applications may result in a low level resultant dopant profile which is only marginally useful for SER reduction. More importantly, the designer must design in the solution, thereby increasing design and fabrication expenses.
FIG. 5 graphically illustrates another shortcoming of retrograded well solution for SER. FIG. 5 is a cross-section of an IC device, similar to that depicted in FIG. 1 above, with a pair of particles passing through the semiconductor at different angles. Semiconductor 500 is depicted as being penetrated by two charged particles, particle 510A traversing semiconductor 500 at an incident angle A, where A 0°, and further with particle 510B traversing semiconductor 500 at incident angle B, where B≠0°. Notice that only the region of high dopant concentration near the bottom of well 513, zone 538, provides any substantial protection from charged particles 512. Any protection achieved by the retrograde is limited only to the area below the well and cannot protect from stray charge migrating from the side of well 513 as illustrated by the arrows. From the depicted illustration, it can be clearly understood that any protection afforded by the region of high dopant concentration in zone 538 near the bottom of well 513 provides protection from charged particles 512 only where the path of the migrating particles would cross or intersect the area in zone 538. Charged particles 512 which have paths that avoid the area in zone 538 may still adversely affect the function of device 508. Even with the design-in expense associated with retrograde well implantation for SER reduction, the solution is flawed.
Thus, even with the prior art's attempt at design-in solutions to the soft error problem evolve, the primary defense to their adverse effects remain in the detection of these errors and subsequent correction due to the inadequate and unpredictable results of those solutions. Detect and correction solutions have been accomplished with on-chip circuitry that continuously performs logic tests to determine whether a logic node has been converted erroneously. Once an error is detected, this circuitry must also perform the correction. The difficulty in this approach is becoming apparent as device geometries continue to decrease. The sensitivity to transient charge due to decreased critical charge, and the increased complexity and density of leading edge IC device designs, make error detection and correction circuitry increasingly prohibitive in terms of complexity and silicon real estate. Moreover, the detection and correction solutions expropriate valuable chip functionality resources that could be allocated to the chip's primary mission, rather than SER reduction role. Thus, such chips are somewhat less efficient and require even more area to provide an equivalent level of mission functionality.